1. Field of the Invention
This invention relates generally to a solid state imager device constructed by charge transfer devices (CTD), and more particularly to a solid state imager device of this kind which has a light receiving area formed of a so-called buried channel MOS structure (the MOS structure designates a stacking structure of semiconductor layer--dielectric layer--conduction layer) to thereby form a charge storage layer on the surface thereof.
2. Description of the Prior Art
In an interline transfer CTD type solid state imager device, it can be expected to remarkably reduce a dark current caused by a current generated on the surface of the device by forming a light receiving section of a buried channel MOS structure to thereby operate the device under conditions that a pinning, i.e. a charge storage layer is formed over the surface thereof.
FIG. 1 shows a cross-sectional view of a main portion of such a solid state imager device which is mainly formed of a silicon semiconductor substrate 1 in which on a substrate forming a p-type region 2 there is formed an n-type semiconductor layer 3. On a major surface 1a of the substrate 1 at the side where the semiconductor layer 3 is provided, there are provided with a light receiving section 4, a charge transfer section 5, i.e. vertical shift register arranged at every vertical line, horizontal shift register, not shown in the drawing, and so on.
The light receiving section 4 is formed of the n-type semiconductor layer 3 and is composed of a light receiving area 6 which is sectioned by channel stop regions, not shown, which are respectively arranged in the horizontal and vertical directions. Further, an n-type overflow drain area or region 8 is arranged adjacent to the light receiving area 6 through a p-type overflow control area or region 7.
The vertical shift register section 5 is formed of an n-type charge transfer region 10 formed on a p-type well region 9 which is selectively formed on the semiconductor layer 3.
Over the major surface 1a of the substrate 1, there is also deposited a light-transmissible dielectric layer 11, e.g. SiO.sub.2 or the like.
There is deposited on the dielectric layer 11 between the light receiving section 4 and the vertical shift register section, i.e. the charge transfer section 5, a transfer control electrode 13 which controls the transfer of signal charges accumulated in the light receiving section 4 to the charge transfer region 10 of the vertical shift register section 5, to thereby form a transfer control section 12. The transfer control electrode 13 is commonly formed e.g. with a portion of transfer electrodes of the vertical shift register section 5.
In a forward portion of the light receiving section 4, that is, on the dielectric layer 11 at the light receiving section 4, there is deposited a light-transmissible forward electrode 14 all over the overflow control region 7 and the overflow drain region 8.
The transfer control electrode 13 and the forward electrode 14 can be formed of e.g. a polycristalline silicon layer. The surface of the device except for the light receiving section 4 is covered with a light shielding member which is not shown in FIG. 1. Further, on the surfaces of the respective electrodes, e.g. the transfer control electrode 13 arranged below the forward electrode 14, there is coated an insulating layer 15 made of e.g. SiO.sub.2 or the like to thereby electrically insulate the respective electrodes one another.
In the construction described above, a predetermined negative voltage is given to the forward electrode 14 to form a storage layer for positive charges in the light receiving area 6 at its surface, so that a buried channel is formed from the suface of the area 6 to its inside. Since the voltage actually applied to the forward electrode 14 is limited by the break down voltage and so on, the lowest potential point in the buried channel is at most several voltages. When charges that is, electrons generated by received light are accumulated in this storage layer, the thickness of a depletion layer produced below the light receiving area 6 is actually at most 2-3 .mu.m. On the other hand, disturbance or a so-called smear in a picked up image, caused by the signal charge flowing from inside the substrate into another light receiving area 6 or the charge transfer region 10 of the vertical shift register section 5 depends on the thickness of the depletion layer below the light receiving area 6 as described above. To be specific, the smear becomes larger as the thickness of the depletion layer is thinner. In general, a depletion layer which has a thickness of only 2-3 .mu.m cannot sufficiently prevent smear from occurring.
Incidentally, a pinning MOS type CCD imager device which has a charge storage layer formed over the surface thereof is disclosed e.g. by a collection of papers presented at '84 National Conference of the Institute of Television Engineers of Japan, on pages 41-42.